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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:52:06 12/02/2009 
-- Design Name: 
-- Module Name:    RegisterFile - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.MIPS_DECODER.ALL;
use WORK.MIPS_REGISTER.ALL;
use WORK.MIPS_MUX.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RegisterFile is
    Port ( Rd_reg1 : in  STD_LOGIC_VECTOR (1 downto 0);
           Rd_reg2 : in  STD_LOGIC_VECTOR (1 downto 0);
           Wr_reg : in  STD_LOGIC_VECTOR (1 downto 0);
           Wr_data : in  STD_LOGIC_VECTOR (15 downto 0);
           RegWrite : in  STD_LOGIC;
           Reg1 : out  STD_LOGIC_VECTOR (15 downto 0);
           Reg2 : out  STD_LOGIC_VECTOR (15 downto 0));
end RegisterFile;

architecture structure of RegisterFile is

	signal data1, data2, data3, data4 : STD_LOGIC_VECTOR (15 downto 0);
	signal wr_en : STD_LOGIC_VECTOR (3 downto 0);

begin
	TwoTo4Decoder : Decoder
					  port map (Wr_reg, wr_en);
	reg_n1 : Reg_16bit
			   port map (RegWrite, wr_en(0), Wr_data, data1);
	reg_n2 : Reg_16bit
			   port map (RegWrite, wr_en(1), Wr_data, data2); 
	reg_n3 : Reg_16bit
			   port map (RegWrite, wr_en(2), Wr_data, data3);
	reg_n4 : Reg_16bit
			   port map (RegWrite, wr_en(3), Wr_data, data4);
	mux1 : Mux
			 port map (data1, data2, data3, data4, Rd_reg1, Reg1);
	mux2 : Mux
			 port map (data1, data2, data3, data4, Rd_reg2, Reg2);

end structure;


library IEEE;
use IEEE.std_logic_1164.all;

package mips_RF is
	component RegisterFile
		Port ( Rd_reg1 : in  STD_LOGIC_VECTOR (1 downto 0);
				Rd_reg2 : in  STD_LOGIC_VECTOR (1 downto 0);
				Wr_reg : in  STD_LOGIC_VECTOR (1 downto 0);
				Wr_data : in  STD_LOGIC_VECTOR (15 downto 0);
				RegWrite : in  STD_LOGIC;
				Reg1 : out  STD_LOGIC_VECTOR (15 downto 0);
				Reg2 : out  STD_LOGIC_VECTOR (15 downto 0));
	end component;
end mips_RF;